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Analysis on High-Performance Full Adders

  • K. V. S. S. S. S. Kavya
  • Bujjibabu PenumuchiEmail author
  • Durgesh Nandan
Conference paper
  • 35 Downloads
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1162)

Abstract

this paper contains the performance analysis of various available designs of full adders. it is observed that the full adder is designed for 1 bit, and later it is extended for 32 bits also. the circuit is designed by using 180 nm technology at 1.8 v supply and technology using 90 nm at 1.2 v supply using cadence virtuoso tools. high speed, low consumption of power, better power–delay product (pdp), layout area, better propagation delay, these are the performance parameters that are compared for various full adders. the circuit performs better in case of improvement of the full adder circuit in terms of parameters like speed and power.

Keywords

Full adder Low power High speed Power–delay product Propagation delay 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2021

Authors and Affiliations

  • K. V. S. S. S. S. Kavya
    • 1
  • Bujjibabu Penumuchi
    • 1
    Email author
  • Durgesh Nandan
    • 2
  1. 1.Department of ECEAditya Engineering CollegeSurampalem, East GodavariIndia
  2. 2.Accendere Knowledge Management Services Pvt. Ltd., CL Educate Ltd.New DelhiIndia

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