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Verification of 32-Bit Memory Using Layered Testbench with Optimum Functional Coverage and Constrained Randomization

  • Sangeeta Parshionikar
  • Sheryl SerraoEmail author
  • Yash Ramesh Kumar
Conference paper
  • 33 Downloads
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1162)

Abstract

体育赛事投注记录as intricacy of electronic designs, chips, asics increases, an efficient, organized and automated approach is required to create testbench. verification using system verilog layered testbench is the systematic way to verify the design without any bugs. also, it checks whether design meets all the specifications correctly. in this paper, a memory model has been implemented and verified by creating real-world verification environment as per design requirement. at top level, scenarios are created, and testbench is broken down to small pieces using classes. verification is carried out using system verilog layered testbench methodology. firstly, verification plan is prepared considering coverage sequences, constrained random stimulus, application of test cases and verification process for memory module. to improve the coverage which is measure of correctness of verification, randomization methodology is used. all input test cases are randomized, and missed or corner cases are covered by directed test cases. mentor graphics questa sim 10.0b is used to carry out simulation. both code and functional coverage are analyzed. our research work achieved 100% code coverage and 85% functional coverage. also, scoreboard and monitor verification blocks are implemented to check the predicted output with actual one.

Keywords

Verification Functional coverage Random stimulus Layered testbench Transactor Monitor Scoreboard 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2021

Authors and Affiliations

  • Sangeeta Parshionikar
    • 1
  • Sheryl Serrao
    • 1
    Email author
  • Yash Ramesh Kumar
    • 1
  1. 1.Department of Electronics, Fr. CRCEMumbai UniversityMumbaiIndia

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